1. Field
The embodiments discussed herein are directed to a communication system. The embodiments discussed herein include a communication system in which parallel transmission is performed between transmission and receiving sides.
2. Description of the Related Art
With the spread of broadband services represented by services via the Internet, a massive amount of digital data is handled in communication networks. Accordingly, data transmission rates and bit rates are increasingly higher. Therefore, there is increasingly a demand for a technique for stabilizing a high-speed signal for transmission.
In general, in the case of transmitting a high bit rate signal between modules or ICs or on a backboard, parallel transmission is performed in which a serial signal is converted to parallel signals and transmitted.
For example, in the field of high-speed optical communication, an interface technique called SFI-5 (Serdes (serializer/deserializer) Framer Interface-5) has been put to practical use. The SFI-5 is a standard for an interface between an optical module and a signal processing LSI or between signal processing LSIs specified by OIF (Optical Internetworking Forum), and a signal transmission range of approximately 40 to approximately 50 Gbps is covered by the standard.
FIG. 17 illustrates an optical communication circuit for which an SFI-5 compliant interface is used. The figure illustrates a schematic configuration of an optical communication circuit 60 for performing approximately 40 Gbps optical communication. The optical communication circuit 60 includes a framer 61, a Serdes section 62, and an optical module 63 (the framer is an LSI for converting an outgoing signal to a transmission frame for a particular network, for example, by converting an Ethernet format signal to a SONET/SDH format signal and outputting the signal, or by converting a SONET/SDH format signal to an Ethernet format signal and outputting the signal). Ethernet is a registered trademark.
When an optical signal is transmitted, signals generated by the framer 61 are transmitted to the Serdes section 62 via multiple transmission lines, and the Serdes section 62 converts the parallel signals to a serial signal. The optical module 63 converts the serial electrical signal to an optical signal, and it outputs an approximately 40 Gbps optical signal via an optical fiber.
Although payload capacity is the essentially same, there may be many different transmission speeds by employing different modulation formats, for example SONET/SDH, Ethernet, OTN, etc. An SFI-5 compliant interface is applied between the framer 61 and the Serdes section 62, and an amount of information corresponding to a total of approximately 40 Gbps is transmitted with the use of sixteen 2.5 Gbps signal lines. As the method for coding exchanged signals, the NRZ (non return to zero) is used in which binary signals transmitted between the sections are indicated with the use of two electrical levels (for example, positive and zero electrical levels).
When parallel transmission is performed, skew (“skew”: propagation delay time difference) occurs among the parallel signals. Therefore, an approximately 2.5 Gbps signal line for deskew is added to suppress the skew. A signal receiving side performs clock recover control with the use of the deskew channel (control for extracting a reproduction clock from the deskew channel), and then aligns the phases of the parallel signals to correspond to one another.
In the SFI-5 as described above, NRZ parallel transmission is performed with the use of sixteen 2.5 Gbps signal lines to handle approximately 40 Gbps transmission. However, an interface method called SFI-5 Phase 2 is also specified by OIF (Optical Internetworking Forum) in which approximately 40 Gbps NRZ parallel transmission is performed with four signal lines (four signal lines plus one deskew signal line in total) by reducing the number of signal lines and increasing the capacity of one signal line to approximately 10 Gbps to enlarge the implementation area for parts.
As a conventional parallel transmission technique, there are proposed techniques for adjusting differences among timings of serial input data of multiple systems by a deskew circuit with a reference signal used as a base, and for converting the timing-adjusted multiple input data to a serial signal by a multiplexer (see Patent Document 1).
Patent Document 1: Japanese Patent Laid-Open No. 2004-228922 (Paragraph Nos. [0011] to [0014] and FIG. 1)
For the current high-speed communication networks, an approximately 40 Gbps communication system has been developed. However, research and development of approximately 100 to 160 Gbps high-speed transmission has been promoted to realize a higher bit rate.
In the case of performing parallel transmission in such high-speed transmission of approximately 100 Gbps or more, the number of parallelized signals is increased to decrease the transmission rate per channel. However, it is not possible to greatly increase the number of parallelized signals because doing so may cause problems such as an increase in space of implementation of transmission lines, an increase in the number of pins of connectors, and an increase in the number of I/Os of an IC.
Consequently, since an increase in the number of parallelized signals is limited even in the case of performing parallel transmission, the transmission capacity per transmission line may be large in the case of high-speed transmission of approximately 100 Gbps or more. Therefore, if a coding method using a broad spectrum bandwidth (frequency bandwidth) like the NRZ used in the SFI-5 is applied to high-speed transmission of approximately 100 Gbps or more, attenuation and intercode interference increase and signals deteriorate, so that codes cannot be correctly transmitted.
Accordingly, applying a multi-level code with a narrow spectrum bandwidth, especially a duo binary code which can be easily code-converted, has been considered. The duo binary code indicates a binary signal to be transmitted using three electrical levels (positive, zero, and negative electrical levels). The duo binary code is not easily subject to intercode interference because the width of the spectrum bandwidth is half or less of the width of the NRZ.
For the reasons described above, for high-speed transmission of approximately 100 to 160 Gbps, both coding of a data channel using a duo binary code, which enables an increase in the transmission rate, and parallel transmission of duo binary-coded signals have been studied.
For deskew processing, a clock is extracted by performing clock recovery control of a duo-binary-coded deskew channel, and phase adjustment of multiple duo-binary signals transmitted in parallel is performed with the use of the extracted clock.
However, although a duo-binary signal has an advantage that the spectrum band width is narrow, there is a problem that, if a circuit is configured so that a duo-binary-coded signal is used as a deskew signal and deskew processing is performed by extracting a clock from the deskew channel as is done conventionally, then the circuit scale is complicated and power consumption increases.
Furthermore, in the case of performing control such as clock recovery from a duo-binary-coded deskew signal, control such as double over-sampling and 8B10B coding may be required, and so there is a possibility that the circuit configuration may become further complicated.